About Me

I am an AI chip architect at ByteDance. I received my Ph.D. degree in Computer Science and Technology at the Institute for Interdisciplinary Information Sciences (IIIS), Tsinghua University (THU), where I was advised by associate Prof. Kaisheng Ma and worked closely with Prof. Dong Xiang and Prof. Torsten Hoefler. I received my B.S. degree in Information Engineering with Zhiyuan honor degree and second bachelor’s degree in Mathematics and Applied Mathematics at Shanghai Jiaotong University (SJTU).

Work Scope (Research Interests)

AI Chip Architectures: AI chip/system SPEC formulation & execution, software-hardware co-design, and preliminary architecture exploration
AI Infrastructures: AI scale-up/out network, distributed training/inference, and performance modeling & profiling
Network Architectures: topology, routing/collective algorithm, protocol, fault tolerance, network-on-chip, chiplet interconnect, optical interconnect (CPO/OCS), NIC, DPU, and switch

News

[July. 2026] Our paper RailX: A Flexible, Scalable, and Low-Cost Network Architecture for Hyper-Scale AI Workloads is accepted by SC 2026 (with an acceptance rate of 19.2%).
[Sep. 2025] I am elected as an Executive Committee Member of the Architecture Professional Committee of the China Computer Federation.
[Sep. 2025] I am awarded the Doctoral Dissertation Award of China Computer Federation (CCF) Architecture Professional Committee (5 in China)
[Jul. 2025] I join ByteDance as an AI chip architect, working on AI chip/infra architecture.
[Jun. 2025] I am awarded the Outstanding Doctoral Dissertation of THU (3 in IIIS, 283 in THU)
[Jun. 2025] I am awarded the Outstanding PhD Graduate of THU (2 in IIIS, 112 in THU)
[May 2025] I defend my doctoral dissertation!

Awards

2025: Doctoral Dissertation Award of CCF Architecture/ CCF体系结构优博 (5 in China)
2025: Outstanding Doctoral Dissertation of THU / 清华大学优秀博士学位论文 (3 in IIIS, 283 in THU)
2025: Outstanding PhD Graduate of THU / 清华大学优秀博士毕业生 (2 in IIIS, 112 in THU)
2025: Endeavor Scholarship / 中国教育发展基金会奋进奖学金 (8 in Tsinghua, 93 in China)
2024: ByteDance Scholarship / 字节跳动奖学金 (15 in China and Singapore)
2024: National Scholarship (PhD) / 博士生国家奖学金 (2 of all CS PhD students in IIIS, THU)
2024: Social Work Excellence Scholarship of THU / 清华大学社会工作优秀奖学金
2023: Integrated Circuit High-Level Urgently-Needed Talents / 中国教育发展基金会集成电路高层次紧缺人才
2023: Comprehensive Excellence Scholarship of THU / 清华大学综合优秀奖学金（一等）
2022: Comprehensive Excellence Scholarship of THU / 清华大学综合优秀奖学金（二等）
2020: Outstanding Graduate of Shanghai / 上海市优秀毕业生 (Top 5%)
2019: National Scholarship (Undergraduate) / 本科生国家奖学金 (2 positions)
2018: Huawei Scholarship of SJTU / 上海交通大学华为奖学金
2017: Three-Good Student of SJTU / 上海交通大学三好学生
2015: First Prize in Chinese Physics Olympiad in Senior / 全国中学生物理竞赛一等奖

Publications

Yinxiao Feng*, Wei Li* (*Co-First), and Kaisheng Ma. Ring Road: A Scalable Polar-Coordinate-based 2D Network-on-Chip Architecture. 57th IEEE/ACM International Symposium on Microarchitecture (MICRO), 2024.

Paper CCF-A, 22.7% (113/497)
Yinxiao Feng and Kaisheng Ma. Switch-Less Dragonfly on Wafers: A Scalable Interconnection Architecture based on Wafer-Scale Integration. International Conference for High Performance Computing, Networking, Storage, and Analysi (SC), 2024.

Paper Code CCF-A, 21.1% (99/470)
Yinxiao Feng, Yuchen Wei, Dong Xiang, and Kaisheng Ma. Evaluating Chiplet-based Large-Scale Interconnection Networks via Cycle-Accurate Packet-Parallel Simulation. USENIX Annual Technical Conference (ATC), 2024.

Paper Code CCF-A, 15.8% (77/488)
Yinxiao Feng, Dong Xiang, and Kaisheng Ma. Heterogeneous Die-to-Die Interfaces: Enabling More Flexible Chiplet Interconnection Systems. 56th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2023.

Paper CCF-A, 23.8% (101/424)
Yinxiao Feng, Dong Xiang, and Kaisheng Ma. A Scalable Methodology for Designing Efficient Interconnection Network of Chiplets. IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2023.

Paper CCF-A, 25% (91/364)
Yinxiao Feng and Kaisheng Ma. Chiplet Actuary: A Quantitative Cost Model and Multi-Chiplet Architecture Exploration. 59th ACM/IEEE Design Automation Conference (DAC), 2022.

Paper Code CCF-A, 23%

Services

Executive Committee Member of the Architecture Professional Committee, CCF